January 2018 prpl Perspectives!
January 2018 prpl Perspectives!
By Art Swift – President, prpl Foundation
Over the past few days, prpl and our member companies Microsemi (https://www.microsemi.com/) and Imperas (http://www.imperas.com/) had the pleasure of attending the sold-out 7th RISC-V workshop held at Western Digital’s conference center in San Jose. Microsemi and Imperas are members of both prpl and the RISC-V foundation. (https://riscv.org/)
For those who don’t know, RISC-V is an open, free instruction set architecture (ISA) developed at the University of California – Berkeley. Support for the new architecture is growing rapidly, as evidenced by the many great presentations from academia and industry, but in certain important areas, RISC-V is still in the early phases of definition, specification, or ecosystem development.
In security for instance, Richard Newell, product architect at Microsemi, is co-chair of a RISC-V task group defining a set of security and cryptographic extensions for the RISC-V ISA. At the workshop, Richard gave two well-received talks. The first, “Security task group update and RISC-V security extension” outlined the current state of the proposed RISC-V security extensions; and the second, “Using Proposed Vector and Crypto Extensions For Fast and Secure Boot,” demonstrated the possibility for some dramatic benefits of these extensions if ratified.
The open and collaborative nature of both the RISC-V and prpl foundations has enabled a hearty exchange of ideas between the groups on security-related industry needs. Richard and his co-chair Joe Xie of NVIDIA recently invited Cesare Garlati, prpl’s chief security strategist, to give a presentation on the prpl security framework https://prpl.works/security-guidance/ to the members of the RISC-V security task group. Cesare was invited back a second time, and we’ve invited Richard to present his RISC-V talk to the prpl virtualization and security working group. We are delighted to work in a friendly collaborative way to make sure that industry best practices for security are adopted across all processor architectures.
Given that many RISC-V based SoCs are now in development, chip simulation is another must-have technology area that the RISC-V ecosystem will need to be successful. It appears that prpl member company Imperas is in “the right place at the right time.” CEO Simon Davidmann took the opportunity at the RISC-V workshop to announce the release of its new RISC-V Processor Developer Suite™ which contains the models and tools necessary to validate and verify the functionality of a RISC-V processor.
As Simon noted in the Imperas press release, “Designing and delivering RISC-V processors is challenging. With the RISC-V Processor Developer Suite, Imperas is providing a solution that accelerates RISC-V development schedules and improves IP quality.”
Congrats to both Microsemi and Imperas for the great showing at the RISC-V workshops! We’re glad to have you participating in both prpl and RISC-V and look forward to the continuing exchange of ideas between the two open source and open standard based foundations!
A well-attended and lively recent ARM TechCon panel explored the topic “Hypervisors: A Real Trend in Embedded, or Just Hype?” Moderated by Brian Bailey of Semiconductor Engineering (R), panelists (L to R) were: Cesare Garlati, prpl Foundation, chief security officer; Simon Davidmann, Imperas Software, founder and CEO; Jack Greenbaum, Green Hills Software, director of engineering, advanced products; and Chris Turner, ARM, Director of Emerging Technology & Strategy.
The panel explored issues around security and functional safety in embedded system development, especially where software touches the hardware. Offering a range of perspectives in the hypervisor ecosystem, panelists addressed changing processor architectures, hardware virtualization extensions and TrustZone, hypervisors, and real time operating systems (RTOSs) as components of the security/safety solution for embedded systems.
This year we were delighted to have had yet another successful OpenWrt Summit! It’s wonderful to see participation grow every year, across both community and industry. We especially thank our gracious local host, Turris Omnia. We also thank our Platinum sponsors: prpl, Inteno, Sentinel, and Intel; and Gold sponsors: CZ.NIC, Sartura, and Technicolor. Without their generous support, use of a comfortable conference center in the beautiful city of Prague would not have been possible.
*** Ask me about free pass and 30% off VIP discount ***
Track 1 – Future Smart Homes 12:00 – 12:40
Panel: Security at the edge: beyond security cameras and doorbells – properly secured devices defending the home
Track 1 – Future Smart Homes 14:20 – 14:40
Presentation: How to Secure the Smart Home from Cyber Threats
Excerpts of my interview with Phil Muncaster @philmuncaster
InfoSecurity Magazine Q4/2017, 4 October 2017
Focus on the Firmware
A cursory look at OWASP’s IoT Security Guidance will highlight just how many elements in the IoT ecosystem could be exploited. Among others, these include the web interface, network, transport encryption layer, mobile app and device firmware. The latter is a key area of focus for the prpl Foundation, a non-profit which is trying to coral the industry into taking a new hardware-based approach to IoT security. Cesare Garlati, Chief Security Strategist, claims that hackers could exploit IoT chip firmware to re-flash the image, allowing them to reboot and execute arbitrary code.
The @ArmTechCon 2017 session today “Hypervisors: A Real Trend in Embedded, or Just Hype?” with Simon Davidmann @ImperasSoftware and Cesare Garlati @prpl_foundation was well-attended and lively!
Then, Cesare came to the Imperas booth #421 for a special session on prpl…