prpl Foundation members talk security and virtual platforms at 7th RISC-V workshop

By Art Swift – President, prpl Foundation

Over the past few days, prpl and our member companies Microsemi (https://www.microsemi.com/) and Imperas (http://www.imperas.com/) had the pleasure of attending the sold-out 7th RISC-V workshop held at Western Digital’s conference center in San Jose. Microsemi and Imperas are members of both prpl and the RISC-V foundation. (https://riscv.org/)

For those who don’t know, RISC-V is an open, free instruction set architecture (ISA) developed at the University of California – Berkeley. Support for the new architecture is growing rapidly, as evidenced by the many great presentations from academia and industry, but in certain important areas, RISC-V is still in the early phases of definition, specification, or ecosystem development.

 

Cesare Garlati, prpl’s chief security strategist and Richard Newell, Microsemi product architect at the 7th RISC-V workshop
Simon Davidmann, CEO of Imperas, during his lightning talk at the 7th RISC-V workshop (photo courtesy of Imperas)

 

 

 

 

 

 

 

In security for instance, Richard Newell, product architect at Microsemi, is co-chair of a RISC-V task group defining a set of security and cryptographic extensions for the RISC-V ISA. At the workshop, Richard gave two well-received talks. The first, “Security task group update and RISC-V security extension” outlined the current state of the proposed RISC-V security extensions; and the second, “Using Proposed Vector and Crypto Extensions For Fast and Secure Boot,” demonstrated the possibility for some dramatic benefits of these extensions if ratified.

The open and collaborative nature of both the RISC-V and prpl foundations has enabled a hearty exchange of ideas between the groups on security-related industry needs. Richard and his co-chair Joe Xie of NVIDIA recently invited Cesare Garlati, prpl’s chief security strategist, to give a presentation on the prpl security framework https://prpl.works/security-guidance/ to the members of the RISC-V security task group. Cesare was invited back a second time, and we’ve invited Richard to present his RISC-V talk to the prpl virtualization and security working group. We are delighted to work in a friendly collaborative way to make sure that industry best practices for security are adopted across all processor architectures.

Given that many RISC-V based SoCs are now in development, chip simulation is another must-have technology area that the RISC-V ecosystem will need to be successful. It appears that prpl member company Imperas is in “the right place at the right time.” CEO Simon Davidmann took the opportunity at the RISC-V workshop to announce the release of its new RISC-V Processor Developer Suite™ which contains the models and tools necessary to validate and verify the functionality of a RISC-V processor.

As Simon noted in the Imperas press release, “Designing and delivering RISC-V processors is challenging. With the RISC-V Processor Developer Suite, Imperas is providing a solution that accelerates RISC-V development schedules and improves IP quality.”

Congrats to both Microsemi and Imperas for the great showing at the RISC-V workshops! We’re glad to have you participating in both prpl and RISC-V and look forward to the continuing exchange of ideas between the two open source and open standard based foundations!

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