New Open Virtual Platforms Processor Models for ARM, Imagination Technologies, RISC-V and Renesas Accelerate Software Development

Latest OVP Models and Virtual Prototype Software Release with iGen, Available Now

Oxford, United Kingdom, May 23, 2017 – Imperas Software Ltd., the leader in high-performance software simulation, today announced the availability of new Open Virtual Platforms (OVP) models for ARM, Imagination Technologies, RISC-V and Renesas processors, along with a new OVPsim software release including the iGen modeling tool.

For embedded software and hardware developers, virtual platforms are increasingly important, especially for multi-core designs. These new OVP library models, for ARM’s ARMv8.1 architecture for the Cortex-A family, Imagination Technologies MIPS I6400, Renesas RH850, and RISC-V, extend Imperas’ leadership in virtual prototyping. OVP models, APIs and the OVPsim virtual platform simulator support development and customization of instruction-accurate platforms for SoCs and larger systems for software development, debug and test.

The Open Virtual Platforms (OVP) portal delivers free, open source models for virtual platforms, as well as OVPsim simulation, and now iGen modeling software. The resources on this portal can significantly accelerate development and test for the embedded software world. New in this OVPsim release is also the iGen productivity tool for peripheral and platform building. All of these processor models are available now.

Rick O’Connor, Executive Director, RISC-V Foundation commented: “Imperas, a member of the RISC-V Foundation, has developed and released open source models of the RISC-V RV32I and RV64I cores through the Open Virtual Platformsä (OVPä) website. These virtual platforms and models enable early software development, long before hardware is available, help lower software development costs, increase quality, improve time to market, and reduce software development risks.”

Fast Processor Models are available as well for the Renesas RH850 microcontroller (MCU) family, commonly used for automotive applications such as power train, braking system and body control. This expands Renesas model support, including previously-released Renesas processor families such as the V850, RL78 and M16C. A video demonstration of OVP Fast Processor models for the Renesas RH8503GM processor and OVPsim, with the Green Hills Software MULTI debugger, is available here.

“Imperas and OVP are proud to provide these new models, along with virtual platforms for embedded software and hardware development,” said Simon Davidmann, president and CEO of Imperas. “And, our new iGen solution significantly accelerates custom model and virtual platform development.”

Imperas virtual prototyping solutions support a wide variety of OVP models and virtual prototypes, including processor models of Altera, ARM (including Cortex-A, R and M families), Imagination Technologies (MIPS), PowerPC, Renesas, RISC-V, Synopsys (ARC) and Xilinx cores. The addition of these new models expands existing Imperas and Open Virtual Platforms (OVP) platform support to over 170 processor models across a wide variety of vendors. For the latest list of Imperas models, please see the OVP website models page.  And follow Imperas on Linked In and twitter @ImperasSoftware.

About Imperas

For more information about Open Virtual Platforms and Imperas, please see www.ovpworld.org and www.imperas.com.

Imperas Virtual Platform Based Software Tools at DAC 2017

Virtual Prototyping in Demonstrations of Software Development Using Continuous Integration and Jenkins, Debug and Test, and a Tutorial on Linux Bring Up on Heterogeneous Multiprocessor SoCs

Oxford, United Kingdom, May 22, 2017 – Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2017, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth in the World of IoT pavilion, booth #521.

DEMO HIGHLIGHTS: See Imperas virtual platform-based solutions for embedded software development, debug, analysis, and verification demos in the World of IoT pavilion, booth #521.

  • Imperas demos will show a wide variety of Open Virtual Platforms (OVP) models and virtual prototypes, with processor models of ARM (Cortex-A, M and R families), Altera, ARC, Imagination Technologies (MIPS), Renesas, RISC-V and Xilinx cores.
  • These demos will showcase the Imperas software Verification, Analysis and Profiling (VAP) tools, including OS-aware tools, plus heterogeneous multiprocessor/multicore debugging capabilities.
  • Imperas will show virtual platforms in a Continuous Integration / Continuous Test embedded software development environment using Jenkins, resulting in an efficient methodology to develop high-quality software.

TUTORIAL: Linux Bring Up on Heterogeneous Multiprocessor SoCs

  • Heterogeneous multiprocessor SoCs are common in applications such as advanced driver assistance systems (ADAS) and autonomous vehicles, networking, industrial automation, security, video analytics and machine learning.  These SoCs often have multiple homogeneous or heterogeneous clusters of CPUs, GPUs, and/or hardware accelerator units that work together on a common set of data. Linux, the general purpose operating system of choice for embedded systems, must be modified for these heterogeneous multi-cluster architectures to support coherence between clusters, as well as differences such as number of processors, processor type, and other features. Vendors often use an open source Linux distribution, then customize for the specific SoC, including drivers for the peripherals, other customizations and unique features.  Obviously, this gets quite complex, and the need to port, customize and bring up Linux on these heterogeneous SoCs requires significant engineering effort.  So how can developers be more efficient?  What are the best practices for Linux porting and bring up on heterogeneous multi-cluster/multiprocessor SoCs?
  • John Min, Solution Engineer at Imagination Technologies, covers components of the basic Linux kernel, device trees and other customizations, SMP variations, static and dynamic drivers, and coherency for multi-cluster architectures.  The methodology used for bring up of the Linux kernel, starting with boot loaders including U-boot, on hardware is presented.
  • Simon Davidmann, CEO of Imperas Software, discusses a robust debug and test environment based on virtual platform technology.  Virtual platforms provide a complementary approach to porting and bring-up on hardware, with benefits of controllability, observability and repeatability. Virtual platforms also enable easy automation of testing, as needed for an Agile Continuous Integration (CI) development and test methodology.  Specific OS-aware tools are also highlighted, plus non-intrusive memory monitors, the use of software assertions, and code and functional coverage techniques for operating systems and drivers.

WHEN AND WHERE: DAC 2017 is June 18-22 at the Austin Convention Center, Austin, Texas.

  • Exhibits are open June 19-21.
  • Imperas tutorial is Monday, June 19 from 10:30am- 12:00pm in room 17AB.

For more information, or to set up meetings with Imperas at DAC, please email sales@imperas.com

About Imperas

For more information about Imperas, please see http://www.imperas.com.

Integrate dynamic voltage and frequency scaling into instruction-accurate virtual platforms

New article in Embedded Computing Design: Integrate dynamic voltage and frequency scaling into instruction-accurate virtual platforms.

In embedded systems, extra-functional requirements, such as power consumption, have been increasing in importance. In a cooperative effort between OFFIS and Imperas Software, the Open Virtual Platforms (OVP) technology has been equipped with support to express and execute dynamic voltage and frequency scaling (DVFS) compatible power models. Software on the virtual platform can access the actual power consumption and perform power management through DVFS. The technology has been successfully demonstrated for an ARM-based multi-core platform, running a synthetic bare-metal DVFS test application and Linux power management.

Read the full article at 

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prpl is Pragmatic for Security

RTC MagazineWithin the prpl Foundation Security Working Group, Imperas is providing solutions for embedded hypervisor/OS developers. Simon Davidmann, Imperas CEO, wrote a guest blog for RTC Magazine, which focusses on embedded computing, including information for both hardware and software developers of embedded systems.

The article is about the security of embedded systems, what the prpl Foundation is doing about it, and what its Virtualization and Security PEG is focused on.

“Most of the public discussion about security presents various aspects of the problems, or a high level view of risks/solutions, or an individual company’s solution to their slice of the problem. The prpl Foundation’s Security Working Group is taking a pragmatic, cross-functional approach to security in embedded devices and systems. What do I mean by pragmatic and cross-functional?…”

Read the full article here.

Imperas active with prpl Foundation at Imagination Technologies Silicon Valley Summit

Simon is prplAt the Imagination Technologies Silicon Valley Summit, a series of presentations and discussions covered Virtualization, Security and the prpl Foundation.

Imperas, as a founding member of the prpl Foundation Virtualization and Security PEG, is working to provide solutions to assist electronic product developers to remove risks associated with embedded software development.

To view the video of  Simon Davidmann, Imperas CEO, click here. 

Imperas, OVP and prpl

OVP diagramThe prpl Foundation recently published its first newsletter, as a way of extending communications with the embedded systems community.  Imperas CEO and Open Virtual Platforms™ (OVP™) founder Simon Davidmann wrote an article for the newsletter, titled “prpl Security Group and Imperas Address IoT Security Challenges via Multi-Domain Virtualization.”  That’s quite the long title.  What was Simon saying?

The full article has more detail, but here’s a summary:

The prpl Security PEG is defining a security roadmap to get from today’s software-virtualized solutions to full hardware supported virtualization, enabling multi-domain security across processors, heterogeneous SoCs and systems built on these technologies including connected devices, routers and hubs. As a provider of tools for embedded software development, Imperas’ unique perspective and added value to the collaborative PEG is in the tools for developing, testing and demonstrating the secure software stack.  Imperas is cooperating with the embedded software providers in the PEG to build Extendable Platform Kits™ (EPKs™) to accelerate development of the individual elements of the secure stack, and enable the easy analysis and verification of these elements in isolation as well as integrated into the complete stack.

The first product of this collaboration is an Extendable Platform Kit (EPK) using an Imperas Open Virtual Platforms (OVP) virtual platform based on the OVP model of the MIPS M5150, with SELTECH’s FEXER OX hypervisor and the Toppers (Tron) real time operating system (RTOS) as three individual guest operating systems (see Figure 2).  EPKs are designed to help users accelerate embedded software development, debug and test.  The platform and peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing peripheral models.

Enjoy reading the article!